Independent hardware project / Design case study
Low-latency FPGA order book engine
An RTL experiment in tracking top-of-book state on an FPGA development board, with hardware-driven traffic generation and on-chip debug tooling.
FPGA
Target platform
X MHz
Clock target
X%
LUT utilization
Quantitative implementation figures are intentionally displayed as placeholders.
Problem and scope
Market data processing benefits from predictable hardware behavior. The aim of this project was to implement a small, instrumented RTL order-book core instead of relying exclusively on a CPU-hosted software pipeline. It is a proof of concept for exploring FPGA architecture and implementation tradeoffs—not a complete exchange feed handler or matching engine.
Architecture
Component
order_gen
Produces test traffic to exercise the datapath without a live market feed.
Component
bbo_tracker
Tracks best-bid and best-offer state in RTL.
Component
lat_profiler
Measures internal processing latency across the monitored path.
Component
uart_tx / ILA
Exports results and supports on-chip signal inspection during development.
Functional module overview, not a cycle-accurate block diagram.
Implementation and measurement
Timing
A generated clock drives the target RTL. Timing closure and functional correctness require separate checks; a target clock frequency alone does not establish system-level performance.
Resource footprint
LUT utilization is tracked after synthesis and implementation. Numerical results are withheld here until they can be published with the corresponding build configuration and reports.
Observability
UART telemetry and integrated logic-analyzer instrumentation support on-chip inspection and functional debugging of the order-book core.
Prototype boundaries
This is a standalone RTL prototype, not a production trading system. It does not implement a complete exchange protocol, networking stack, or live-feed integration.
Public reproducibility will require a buildable RTL repository, test vectors, reference-model checks, and implementation reports tied to a documented configuration.
Next engineering steps
- Add deterministic, replayable order sequences and reference-model checks.
- Publish timing constraints and resource-utilization reports with the tested configuration.
- Extend the datapath toward book-derived signals such as order-flow imbalance and VWAP.
- Publish a reproducible RTL repository and build instructions once ready.
Code is not linked here because a verified public repository for this specific project has not been provided.