I'm Jayden, a computer engineering student at Texas A&M working across RISC-V architecture, FPGA/RTL design, ASIC design verification, and embedded security.
From processor verification to FPGA prototypes and full-stack systems, I work where software meets the hardware it relies on.
Texas A&M University · B.S. Computer Engineering · Dec 2027
Current work: R&D at Sandia · Formal and functional ASIC verification at Rev Silicon
6
RISC-V security bugs found
Research with SETH Lab
2×
Hardware fuzzing coverage on RISC-V cores
Compared with TheHuzz USENIX 2022
01 / PUBLIC WORK
Technical depth, the design decisions behind it, and the evidence available to inspect.
Built an FPGA order-book prototype on an Arty A7-35T, with best-bid/offer tracking, hardware-generated test traffic, and on-chip debugging instrumentation.
$ fuzz --target riscv --coverage
[+] coverage-guided exploration
[+] 6 security bugs discovered
[+] coverage vs. baseline: 2×
$ _
Investigated security bugs in open-source RISC-V processors, combining architectural understanding with simulation and guided test generation. Research yielded six bugs and 2× coverage compared with a prior fuzzing baseline.
Lead infrastructure and web integration for a student-run investment platform, connecting automated brokerage-report ingestion, market-data APIs, and portfolio visibility. Systematize deployment and operations across AWS and Texas A&M cloud infrastructure, while maintaining engineering journals, technical documentation, and standardized operational workflows to support team continuity and reliable system maintenance.
RSD / ISA conformance
4
FP status and context-state findings
2
CSR privilege and access findings
Technical investigation of six reported ISA-conformance findings in the RSD out-of-order processor. Compared RISC-V architectural rules with RTL simulation evidence, focusing on floating-point context state, CSR privilege checks, and exception handling. These are the findings associated with the processor fuzzing research above, not additional discoveries.
Public data project aggregating computer-security conference publications into browsable research rankings.
View source code
Shipped a web application for identifying written languages, with multilingual content and an interactive game interface.
View source code
02 / EXPERIENCE
Public descriptions are deliberately limited where employer work is confidential.
May 2026 — present
R&D Engineering Intern
Year-round research internship. Project details are not publicly disclosed.
2026
ASIC Design Verification
Formal and functional design verification of an AI accelerator ASIC being prepared for tapeout. Working on RTL correctness without disclosing implementation details.
Spring 2026
Software Engineering Intern
Embedded software internship. Project details are not publicly disclosed.
2024 — 2025
Undergraduate Researcher / Hardware Security Intern
RISC-V processor fuzzing research; discovered six processor security bugs and evaluated coverage against existing approaches.
Public write-upSummers 2023 & 2024
Embedded Security Intern / BWSI Instructor
Worked on embedded security education and secure firmware concepts; led a team of eight instructors.
Also: Academic Instructor, Texas A&M Cohort in Hardware Security · Security Engineering, TAMU Cybersecurity Center · Director, idekCTF.
03 / BACKGROUND
I study computer engineering at Texas A&M University, with minors in mathematics and cybersecurity. My interests center on processor microarchitecture, formal and functional ASIC verification, FPGA systems, and trustworthy embedded software.
I enjoy work that connects RTL, operating systems, and the application above them. Outside of research, I've organized security competitions and built tools used by other engineers and students.
CONTACT
I'm interested in challenging hardware design, verification, FPGA, and embedded systems problems.